The present invention relates generally to memory circuits, and more specifically to a method and apparatus for performing selected data reads from a memory array.
Processing systems typically rely on memory structures to store data that is being processed. Such memory structures are often individual integrated circuits coupled to the processing circuitry. For a read operation that retrieves data from the memory, an address is applied to the memory circuit, and the data stored at that location is provided back to the requesting entity. The number of bits provided back to the requesting entity is typically based on the width of the data bus connecting the processor and the memory.
In some systems, it may be efficient to store related data in close addressing proximity within the memory array that supports the processing system. For example, in a graphics processing system that supports three-dimensional (3D) graphics processing, the frame buffer, which is stored in memory, typically stores color data and Z data for each pixel location. The Z data represents a depth coordinate value for the particular pixel location, where the depth is used in rendering operations to determine if a graphics primitive overlaps pixel data currently stored in the frame buffer, therefore modifying the color to be displayed for that pixel location. In order to facilitate blending operations in a video graphics processing system, the color data and the Z data for a pixel location may be stored together in the memory array. When the memory array is a dynamic random access memory (DRAM) array, block reads may be performed, where a block read provides color and Z data corresponding to a number of pixel locations.
As pixel processing rates increase, the available bandwidth on the bus structures that exchange data between a graphics processor and a memory circuit that stores the frame buffer can become a bottleneck in terms of the maximum pixel processing rate that can be achieved. Although additional signal lines can be added to these data buses to improve the data exchange rate, the additional pins on the integrated circuits required to support these signal lines add significant cost to the integrated circuits.
In many cases, the data retrieved from the memory circuit through a block transfer may include portions that are not needed by the graphics processor or similar processing circuit. However, due to the fact that block fetches occur, this data is retrieved along with the desirable data. As such, a portion of the limited bus bandwidth that is available is effectively wasted. For example, if color data is all that is desired by the graphics processor, which may be the case for generation of a display signal, retrieval of the Z data for each of the pixel locations through block transfers from the memory circuit to the graphics processor wastes valuable bandwidth on the bus.
Therefore, a need exits for a method and apparatus for performing selected data reads from a memory such that available bandwidth over interconnecting bus structures is efficiently utilized.